View STAC9721T_403746.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
SigmaTel, Inc.
Integrating Mixed-Signal Solutions
STAC9721/23
Stereo AC'97 Codec With Multi-Codec Option
GENERAL DESCRIPTION:
SigmaTel's STAC9721/23 is a general-purpose 18-bit stereo, full duplex, audio codec that conforms to the analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.1). The STAC9721/23 incorporates SigmaTel's proprietary Sigma-Delta technology to achieve a DAC SNR in excess of 95dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. Also included are SigmaTel's 3D stereo enhancement (SS3D), and an extra true line-level out for headphones or speaker amplifiers. The STAC9721/23 may be used as a secondary codec, with the STAC9700/04/07/44/45 or a 4-channel STAC9708 as the primary, in multiple codec configurations conforming to the AC'97 Rev. 2.1 specification. This configuration can provide up to six-channel output, providing AC-3 playback for DVD applications. The STAC9721/23 communicates via the five-wire ACLink interface with any AC-Link capable controller or advanced core logic chip-set. Packaged in an AC'97 compliant 48-pin TQFP, the STAC9721/23 can be placed on motherboards, daughter boards, addon cards or AMR/MDC cards.
FEATURES:
* * * * * * * High performance technology Energy saving power down modes 18-bit full duplex stereo ADC, DACs AC-Link protocol compliance 3.3V Multiple power supply options Pin compatible with the STAC9700/44/45 SigmaTel Surround (SS3D) Stereo Enhancement * * * * * * EAPD - External Amplifier Power Down Control Multi-Codec option (Intel AC'97 rev 2.1) Six analog line-level inputs 48-pin TQFP LINE-to-LINE SNR 102dB The STAC9723 is tested at +3.3V
ORDERING INFORMATION:
PART NUMBER
STAC9721T STAC9723T
PACKAGE
48-pin TQFP 7mm x7mm x 1.4mm 48-pin TQFP 7mmx7mm x 1.4mm
TEMPERATURE RANGE
0o C to +70o C 0o C to +70o C
SUPPLY RANGE
DVdd = 3.3V or 5V, AVdd = 5V DVdd = 3.3V, AVdd = 3.3V
SigmaTel reserves the right to change specifications without notice
1
04/07/00
SigmaTel, Inc.
Table of Contents
Data Sheet
9.6 9.7 10.1 10.2 10.3 10.4 10.5 10.6
STAC9721
AC-LINK LOW POWER MODE 36 ATE TEST MODE MAXIMUM RATINGS: POWER CONSUMPTION AC-LINK STATIC DIGITAL STAC9721 ANALOG STAC9723 ANALOG 37 38 39 41 41 43
GENERAL DESCRIPTION:.........................1 TABLE OF CONTENTS................................2 TABLE OF CONTENTS - FIGURES ..........3 1. PIN/SIGNAL DESCRIPTIONS .............7
10. ELECTRICAL SPECIFICATIONS: ...38
RECOMMENDED CONDITIONS 38
1.1 1.2 1.3 1.4
2.
DIGITAL I/O ANALOG I/O FILTER/REFERENCES/GPIO
7 8 9
POWER AND GROUND SIGNALS 9 CLOCKING RESET AC-LINK SERIAL INTERFACE 10 10
AC-LINK ................................................10
APPENDIX A ................................................45 APPENDIX B ................................................46
2.1 2.2
3.
DIGITAL INTERFACE........................11
TABLE of Tables
Table 1. Package Dimensions Table 2. Pin Designation Table 3. Digital Signal List Table 4. Analog Signal List Table 5. Filtering and Voltage References Table 6. Mixer Functional Connections Table 7. Programming Registers Table 8. Play Master Volume Register Table 9. PC_BEEP Register Table 10. Analog Mixer Input Gain Register Table 11. Record Select Control Registers Table 13. Record Gain Registers Table 14. General Purpose Register Table 15. 3D Control Registers not defined. Table 16. Powerdown Status Registers Table 17. Extended Audio ID Functions Table 19: Analog Current Adjust Table 16. Multi-Channel Programming Table 18. Low Power Modes Table 19. Codec ID Selection Table 20. Secondary Codec Register Access
2
3.1 3.2
4.
11
4 4 7 8 9 20 21 22 22 23 23 24 24 Error! Bookmark 25 26 27 28 29 31 32
AC-LINK LOW POWER MODE 18 MIXER INPUT MIXER OUTPUT PC BEEP IMPLEMENTATION PROGRAMMING REGISTERS: 20 20 20 21
STAC9721/23 MIXER ...........................19
4.1 4.2 4.3 4.4
5. 6.
LOW POWER MODES ........................29 MULTIPLE CODEC SUPPORT .........31
6.1 6.2
7. 8.
PRIMARY/SECONDARY CODEC 31 SECONDARY CODEC ACCESS 32
Table 12. Left Record Select Control Registers 23
TESTABILITY ......................................32 EXTENDED FUNCTIONALITY ........33
8.1
9.
ANTI-POP CIRCUITRY COLD RESET WARM RESET CLOCKS DATA SETUP AND HOLD SIGNAL RISE AND FALL
33 33 34 34 35 35
AC TIMING CHARACTERISTICS .33
9.1 9.2 9.3 9.4 9.5
04/07/00
04/07/00
SigmaTel, Inc.
Table 21. Cold Reset Table 22. Warm Reset Table 23. Clocks Table 24. Data Setup and Hold Table 25. Signal Rise and Fall Times
Data Sheet
33 34 34 35 35 36 37 38
STAC9721
Figure 2. STAC9721/23 Block Diagram............... 5 Figure 3. AC-Link to its companion controller .. 10 Figure 4. Bi-directional Audio Frame ................. 12 Figure 5. AC-Link Audio Output Frame .......... 12 Figure 6. Start of an Audio Output Frame ....... 13 Figure 7. STAC9721/23 Audio Input Frame ..... 16 Figure 8. Start of an Audio Input Frame ........... 16 Figure 9. STAC9721/23 Powerdown Timing ..... 18 Figure 10. STAC9721/23 Mixer ......................... 19 Figure 11. Powerdown/Powerup flow.................. 29 Figure 12. Powerdown/Powerup flow ................. 30 Figure 13. Cold Reset........................................... 33 Figure 14. Warm Reset ........................................ 34 Figure 15. Clocks.................................................. 34 Figure 16. Data Setup and Hold.......................... 35 Figure 17. Signal Rise and Fall Times ................ 35 Figure 18. AC-Link Low Power Mode Timing.. 36 Figure 19. ATE Test Mode .................................. 37
Table 26. AC-Link Low Power Mode Timing Table 27. ATE Test Mode Table 28. Operating Conditions Table 33: Power Consumption 39
Table 34: Power Consumption at 3.3V Analog 39 Table 35: Reduced Analog Power Settings Table 30. AC-Link Static Specifications 40 41
Table 31. Analog Performance Characteristics 41 Table 32. Analog Performance Characteristics 43
Table of Contents - Figures
Figure 1. Package Outline ..................................... 4
3 04/07/00
04/07/00
SigmaTel, Inc.
Figure 1. Package Outline
D D1
26 38
Data Sheet
STAC9721
Table 1. Package Dimensions Key TQFP Dimensions 9.00 mm 7.00 mm 9.00 mm 7.00 mm 0.20 mm 0.50 mm 1.4 mm
a e
SigmaTel
E E1
48 pin TQFP
14 2
D D1 E E1 a (lead width) e (pitch) thickness
Table 2. Pin Designation PIN # 1 2 3 4 5 6 7 8 9 10 11 12 Signal Name DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP PI N# 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R PIN # 25 26 27 28 29 30 31 32 33 34 35 36 Signal Name AVdd1 AVss1 Vref Vrefout AFILT1 AFILT2 CAP1 CAP2 CAP3 APOP LINE_OUT_L LINE_OUT_R PIN # 37 38 39 40 41 42 43 44 45 46 47 48 Signal Name MONO_OUT AVdd2 LNLVL_OUT_L NC LNLVL_OUT_R AVss2 NC NC CID0 CID1 EAPD NC
# denotes active low
4 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
4 stereo sources 2 mono sources mono stereo
PCM out DACs 48Kss
STAC9721
Power Management
LNLVL_OUT MIXER
Analog mixing and Gain control
Mic Boost 0/20 dB M U X
AC-link
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET
Digital Interface
DAC DAC
LINE_OUT MONO_OUT MIC1 MIC2
Registers 64 x 16 bits
PCM in ADCs
ADC ADC
48Kss
Figure 2. STAC9721/23 Block Diagram
The STAC9721/23 block diagram is illustrated above. It performs fixed 48K sample rate D-A & A-D conversion, mixing, and analog processing. The digital interface communicates with the AC'97 controller via the five wire AC-Link and contains the 64 word by 16-bit registers. Two, fixed 48Ks/s DAC's support two stereo PCM-out channels. The digital mix of all software sources, including the internal synthesizer and any other digital sources, is performed in the digital controller. The Mixer block mixes the PCM_OUT with any analog sources, then outputs to LINE_OUT and LNLVL_OUT. The MONO_OUT delivers either mic only or a mono mix of sources from the mixer. The two fixed 48Ks/s ADC's take any mix of mono or stereo sources and convert it to a stereo PCM-in signal. All ADC's and DAC's operate at 18-bit resolution. The STAC9721/23 is designed primarily to support stereo, 2-speaker audio. However, true AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option in the STAC9721/23. Using this option with a STAC9704/07/21/23 or the 4-channel STAC9708 as the primary codec, and the STAC9721/23 as the secondary codec, 6-channel output can be achieved in an AC'97 architecture. Also, the STAC9721/23 provides for a stereo enhancement feature, SigmaTel Surround 3D or SS3D. SS3D provides the listener with several options to expand the soundstage beyond the normal 2speaker arrangement. Together, with the logic component (controller or advanced core logic chip-set) of AC'97, the STAC9721/23 can be SoundBlaster and Windows Sound System compatible. SoundBlaster is a registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation.
5 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
Figure 3. Connection Diagram - See Appendix A for an alternative connection diagram when using separate supplies. See Appendix B for specific connection requirements prior to operation.
2 ohm * Ferrite Bead *
* Suggested
3.3V or 5V 5% 0.1uF
0.1uF
0.1uF 1uF 0.1uF 38 AVdd2 1 DVdd1
10uF
25 AVdd1
9 DVdd2 XTL_IN 2 27pF
12 13 14
24.576MHz PC BEEP XTL_OUT PHONE AUX_L 3 27pF SDATA_OUT BIT_CLK SDATA_IN SYNC RESET CID0 CID1 5 6 8 10 11 45 46
_
22 ohms
15 16
AUX_R VIDEO_L
SigmaTel
EMI Filter
27pF
17
18
VIDEO_R CD_L
STAC9721/23
19
20
CD_GND CD_R MIC1 Vref 27 0.1uF Vrefout 28 1uF
21
22
MIC2 CAP1 31 33
Optional Anti-Pop Circuit
23
LINE_IN_L
CAP3
10uF 100uF
24 32 0.1uF
LINE_IN_R
APOP CAP2 EAPD LINE_OUT_L 47 35 36 37 34
1uF
820pF
29
LINE_OUT_R AFILT1 MONO_OUT AFILT2
820pF
30
AVss1
26
AVss2 42
DVss1 4
DVss2 7
LNLVL_OUT_L 39
LNLVL_OUT_R 41
** Teminate ground plane as close to power supply as possible
NOTE: Pins 31, 33, 34, 40
43, 44, and 48 are No Connects Analog Gnd Digital Gnd
6 04/07/00
04/07/00
SigmaTel, Inc.
1. PIN/SIGNAL DESCRIPTIONS
Data Sheet
STAC9721
1.1 Digital I/O
These signals connect the STAC9721/23 to its AC'97 controller counterpart, an external crystal, multicodec selection and external audio amplifier.
Table 3. Digital Signal List Signal Name RESET # XTL_IN XTL_OUT SYNC BIT_CLK SDATA_OUT SDATA__IN CID0 CID1 EAPD
# denotes active low
Type I I O I O I O I I O
Description AC'97 Master H/W Reset 24.576 MHz Crystal 24.576 MHz Crystal 48 kHz fixed rate sample sync 12.288 MHz serial data clock Serial, time division multiplexed, AC'97 input stream Serial, time division multiplexed, AC'97 output stream Multi-Codec ID select - bit 0 Multi-Codec ID select - bit 1 External Amplifier Power Down
7 04/07/00
04/07/00
SigmaTel, Inc.
1.2 Analog I/O
Data Sheet
STAC9721
These signals connect the STAC9721/23 to analog sources and sinks, including microphones and speakers.
Table 4. Analog Signal List Signal Name PC-BEEP PHONE MIC1 MIC2 LINE-IN-L LINE-IN-R CD-L CD-GND CD-R VIDEO-L VIDEO-R AUX-L AUX-R LINE-OUT-L LINE-OUT-R MONO-OUT LNLVL_OUT_ L LNLVL_OUT_ R Type I I I I I I I I I I I I I O O O O O Description PC Speaker beep pass-through From telephony subsystem speakerphone (or DLP - Down Line Phone) Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel CD Audio Left Channel CD Audio analog ground CD Audio Right Channel Video Audio Left Channel Video Audio Right Channel Aux Left Channel Aux Right Channel Line Out Left Channel Line Out Right Channel To telephony subsystem speakerphone (or DLP - Down Line Phone) True Line Level Out Left Channel True Line Level Out Right Channel
* Note: any unused input pins should be tied together and connected to ground with a capacitor (0.1 uF suggested), except the MIC1 and MIC2 inputs which require their own 0.1 uF capacitors to ground if not used.
8 04/07/00
04/07/00
SigmaTel, Inc.
1.3 Filter/References/GPIO
Data Sheet
STAC9721
These signals are connected to resistors, capacitors, specific voltages, or provide general purpose I/O.
Table 5. Filtering and Voltage References Signal Name Vref Vrefout AFILT1 AFILT2 CAP1 CAP2 CAP3 APOP EAPD Type O O O O O O O O O Description Reference Voltage Reference Voltage out 5mA drive (intended for mic bias) Anti-Aliasing Filter Cap - ADC channel Anti-Aliasing Filter Cap - ADC channel Analog Output Hold-Off Delay ADC reference Cap Anti-Pop Power Sustain Delay Anti-Pop Output Ground Shunt Control External Amplifier Power Down Control
1.4 Power and Ground Signals
Table 6. Power Signal List STAC9721/23 Signal Name AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 Type I I I I I I I I STAC9721 Analog Vdd = 5.0V Analog Vdd = 5.0V Analog Gnd Analog Gnd Digital Vdd = 5.0V or 3.3V Digital Vdd = 5.0V or 3.3V Digital Gnd Digital Gnd STAC9723 Analog Vdd = 3.3V Analog Vdd = 3.3V Analog Gnd Analog Gnd Digital Vdd = 3.3V Digital Vdd = 3.3V Digital Gnd Digital Gnd
9 04/07/00
04/07/00
SigmaTel, Inc.
2. AC-LINK
Data Sheet
STAC9721
Below is the figure of the AC-Link point to point serial interconnect between the STAC9721/23 and its companion controller. All digital audio streams and command/status information are communicated over this AC-Link. Please refer to the "Digital Interface" section 3 for details.
Figure 3. STAC9721/23's AC-Link to its companion controller
XTAL_IN
SYNC
Digital DC'97 Controller
BIT CLK
SDATA_OUT SDATA_IN RESET
XTAL_OUT
SigmaTel
AC'97 Codec
2.1 Clocking
STAC9721/23 derives its clock internally from an externally connected 24.576 MHz crystal or an oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the BIT_CLK pin at 12.288 MHz (half of crystal frequency). The beginning of all audio sample packets, or "Audio Frames", transferred over AC-Link is synchronized to the rising edge of the "SYNC" signal driven by the AC'97 controller. Data is transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each immediately following falling edge of BIT_CLK.
2.2 Reset
There are 3 types of resets as detailed under "Timing Characteristics". * * * "cold" reset where all STAC9721/23 logic and registers are initialized to their default state "warm" reset where the contents of the STAC9721/23 register set are left unaltered "register" reset which only initializes the STAC9721/23 registers to their default states
After signaling a reset to the STAC9721/23, the AC'97 controller should not attempt to play or capture audio data until it has sampled a "Codec Ready" indication via register 26h from the STAC9721/23. For proper reset operation SDATA_OUT should be "0" during "cold" reset. See "Testability" section for more information.
10 04/07/00
04/07/00
SigmaTel, Inc.
3. DIGITAL INTERFACE
Data Sheet
STAC9721
3.1 AC-Link Digital Serial Interface Protocol
The STAC9721/23 communicates to the AC'97 controller via a 5-pin digital serial AC-Link interface, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands and status information are communicated over this point-to-point serial interconnect. The AC-Link handles multiple inputs, and output audio streams, as well as control register accesses using a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data transaction. The following data streams are available on the STAC9721/23: PCM Playback PCM Record data Control Status 4 output slots 2 input slots 2 output slots 2 input slots 4 Channel composite PCM output stream 2 Channel composite PCM input stream Control register write port Control register read port
Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9721/23 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of ACLink data, STAC9721/23 for outgoing data and AC'97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK. The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "tagged" invalid, it is the responsibility of the source of the data (STAC9721/23 for the input stream, AC'97 controller for the output stream) to stuff all bit positions with 0's during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals can be halted.
11 04/07/00
04/07/00
SigmaTel, Inc.
SYNC OUTGOING STREAMS INCOMING STREAMS TAG PHASE
TAG CMD ADR STATUS ADR
Data Sheet
STAC9721
CMD DATA STATUS DATA
PCM LEFT PCM LEFT
PCM RT
NA
PCM CTR
PCM LSURR
PCM RSURR
PCM LFE
PCM LALT
PCM RALT
RSVD
TAG
PCM RT
NA
NA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DATA PHASE
Figure 4. AC'97 Standard Bi-directional Audio Frame
3.1.1
AC-Link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9721/23 DAC inputs, and control registers. Each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the STAC9721/23 indicate which of the corresponding 12 times slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate. The following diagram illustrates the time slot based AC-Link protocol.
Figure 5. AC-Link Audio Output Frame
Data Phase Tag Phase 20.8 uS (48 kHZ)
SYNC BIT_CLK SDATA_OUT
12.288 MHz
valid Frame
slot1
slot2
slot(12) "0"
CID1 CID0
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12
e
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9721/23 samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9721/23 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
12 04/07/00 04/07/00
SigmaTel, Inc.
Data Sheet
Figure 6. Start of an Audio Output Frame
SYNC assertion here
STAC9721
SYNC
first SDATA_OUT bit of frame here
BIT_CLK SDATA_OUT
valid Frame
slot1
slot2
End of previous audio frame
SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0's by the AC'97 controller. . When mono audio sample streams are sent from the AC'97 controller it is necessary that BOTH left and right sample stream time slots be filled with the same data.
3.1.1.1 Slot 1: Command Address Port
The command port is used to control features, and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9721/23 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Audio output frame slot 1 communicates control register address, and write/read command information to the STAC9721/23. Command Address Port bit assignments: Bit (19) Read/Write command (1= read, 0=write) Bit (18:12) Control Register Index (64 16-bit locations, addressed on even byte boundaries) Bit (11:0) Reserved (Stuffed with 0's) The first bit (MSB) sampled by STAC9721/23 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must he stuffed with 0's by the AC'97 controller.
3.1.1.2 Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by Slot 1, bit 19) Bit (19:4) read) Bit (3 :0)
04/07/00
Control Register Write Data Reserved
13
(Stuffed with 0's if current operation is a
(Stuffed with 0's)
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
If the current command port operation is a read then the entire slot time must be stuffed with 0's by the AC'97 controller.
3.1.1.3 Slot 3: PCM Playback Left Channel
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (by the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.4 Slot 4: PCM Playback Right Channel
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (by the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.5 Slot 5: Reserved
Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9721/23.
3.1.1.6 Slot 6: PCM Center Channel
Audio output frame slot 6 is the composite digital audio center stream used in a multichannel application where the STAC9721/23 has been programmed to accept the DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.7 Slot 7: PCM Left Surround Channel
Audio output frame slot 7 is the composite digital audio left surround stream used in a multi-channel application where the STAC9721/23 has been programmed to accept the DAC PCM data from slots 7 and 8. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.8 Slot 8: PCM Right Surround Channel
Audio output frame slot 8 is the composite digital audio right surround stream used in a multi-channel application where the STAC9721/23 has been programmed to accept the DAC PCM data from slots 7 and 8. Please refer to the register programming section for details on the multi-channel programming options.
14 04/07/00 04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
3.1.1.9 Slot 9: PCM Low Frequency Channel
Audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the STAC9721/23 has been programmed to accept the DAC DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi-channel programming options.
3.1.1.10 Slot 10: PCM Alternate Left
Audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel application where the STAC9721/23 has been programmed to accept the DAC PCM data from slots 10 and 11. Please refer to the register programming section for details on the multi channel programming options.
3.1.1.11 Slot 11: PCM Alternate Right
Audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-channel application where the STAC9721/23 has been programmed to accept the DAC PCM data from slots 10 and 11. Please refer to the register programming section for details on the multi channel programming options.
3.1.1.12 Slot 12: Reserved
Audio output frame slot 12 is reserved for modem operations and is not used by the STAC9721/23.
3.1.2
AC-Link Audio Input Frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. As is the case for audio output frame, each ACLink audio input frame consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9721/23 is in the "Codec Ready" state or not. If the "Codec Ready" bit is a 0, this indicates that STAC9721/23 is not ready for normal operation. This condition is normal following the de-assertion of power on reset, for example, while STAC9721/23's voltage references settle. When the AC-Link "Codec Ready" indicator bit is a 1, it indicates that the AC-Link and STAC9721/23 control/status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control Status Register index 26h (refer to Mixer Register section) to determine exactly which subsections, if any, are ready. Prior to any attempts at putting STAC9721/23 into operation the AC'97 controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9721/23 has become "Codec Ready". Once the STAC9721/23 is sampled "Codec Ready", the next 12 bit positions sampled by the AC'97 controller indicate which of the
15 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
corresponding 12 time slots are assigned to input data streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link protocol.
Figure 7. STAC9721/23 Audio Input Frame
Data Phase Tag Phase 20.8 uS (48 kHZ)
SYNC BIT_CLK SDATA_IN
12.288 MHz
valid Frame
slot1
slot2
slot(12) "0"
"0"
"0"
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9721/23 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9721/23 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 8. Start of an Audio Input Frame
SYNC assertion here
SYNC
first SDATA_OUT bit of frame here
BIT_CLK SDATA_IN
Codec Ready
slot1
slot2
End of previous audio frame
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by STAC9721/23. SDATA_IN data is sampled on the falling edges of BIT_CLK.
3.1.2.1 Slot 1: Status Address Port
The status port is used to monitor status for STAC9721/23 functions including, but not limited to, mixer settings, and power management.
16 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by STAC9721/23 during slot 0) Status Address Port hit assignments: Bit (19) Bit (18;12) returned) Bit (11:0) RESERVED Stuffed with 0) Control Register Index (Echo of register index for which data is being RESERVED (Stuffed with 0's)
The first bit (MSB) generated by STAC9721/23 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0's by STAC9721/23.
3.1.2.2 Slot 2: Status Data Port
The status data port delivers 16-bit control register read data. Bit (19:4) Control Register Read Data (Stuffed with 0's if tagged "invalid") Bit (3 :0) RESERVED (Stuffed with 0's) If Slot 2 is tagged "invalid" by STAC9721/23, then the entire slot will be stuffed with 0's. Slot 3: PCM Record Left Channel Audio input frame slot 3 is the left channel output of STAC9721/23 input MUX, postADC. STAC9721/23 ADCs are implemented to support 18-bit resolution. STAC9721/23 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot.
3.1.2.3 Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9721/23 input MUX, postADC. STAC9721/23 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot.
3.1.2.4 Slots 5-12: Reserved
Audio input frame slots 5-12 are not used by the STAC97908/11 and are always stuffed with 0's.
17 04/07/00
04/07/00
SigmaTel, Inc.
3.2 AC-Link Low Power Mode
Data Sheet
STAC9721
The STAC9721/23 AC-Link can be placed in the low power mode by programming register 26h to the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage level. The AC'97 controller can wake up the STAC9721/23 by providing the appropriate reset signals.
Figure 9. STAC9721/23 Powerdown Timing
SYNC BIT_CLK SDATA_OUT
slot2 per frame TAG Write to 0x20 Data PR4
SDATA_IN
slot2 per frame
TAG
Note: BIT_CLK not to scale
BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at the point where it is ready to program the AC-Link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). The AC'97 controller should also drive SYNC and SDATA_OUT low after programming the STAC9721/23 to this low power mode.
3.2.1
Waking up the AC-Link Once the STAC9721/23 has halted BIT_CLK, there are only two ways to "wake up" the AC-Link. Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a "Cold AC'97 Reset", and a "Warm AC'97 Reset". The current power down state would ultimately dictate which form of reset is appropriate. Unless a "cold" or "register" reset (a write to the Reset register) is performed, wherein the AC'97 registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. When AC-Link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15). Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time. By driving RESET# low, BIT_CLK, and SDATA_IN will be activated, or reactivated as the case may be, and all STAC9721/23 control registers will be initialized to their default power on reset values. Note: RESET# is an asynchronous input. # denotes active low
18 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9721/23 register values. A warm reset is signaled by driving SYNC high for a minimum of 1us in the absence of BIT_CLK. Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9721/23.
4.
STAC9721/23 MIXER
The STAC9721/23 mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. These include: * * * * * * System Audio: digital PCM input and output for business, games and multimedia CD/DVD: analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer Mono microphone: choice of desktop mic, with programmable boost and gain Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing Video: TV tuner or video capture card with internal connections to Codec mixer AUX/synth: analog FM or wavetable synthesizer, or other internal source
PCM out
D/A PC_Beep Phone
vol vol vol 20dB vol vol vol vol vol
mute mute mute mute mute mute mute mute
3D
Analog Audio Sources
MIC1 MIC2 LINE IN CD Video AUX
-6dB
LNLVL Volume Master Volume Mono Volume
LNLVL_OUT
3D
-6dB
LINE_OUT MONO_OUT
MUX
KEY
M Analog ono Stereo Analog Digital
Figure 10. STAC9721/23 Mixer Functional Diagram
MUX
Master Input Volume
A/D A/D
PCM IN
19 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
Table 6. Mixer Functional Connections
STAC9721
Source PC_Beep PHONE MIC1 MIC2 LINE_IN CD VIDEO AUX PCM out LINE_OUT LNLVL_OUT MONO_OUT PCM in
Function PC beep pass thru speakerphone or DLP in desktop microphone second microphone external audio source audio from CD-ROM audio from TV tuner or video camera upgrade synth or other external source digital audio output from AC'97 Controller stereo mix of all sources Additional stereo mix of all sources MIC or mix for speakerphone or DLP out digital audio input to AC'97 Controller
Connection from PC beeper output from telephony subsystem from MIC jack from second MIC jack from line-in jack cable from CD-ROM cable from TV or VidCap card internal connector AC-Link To output jack To output jack to telephony subsystem AC-Link
4.1 Mixer Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9721/23 supports the following input sources: * * * any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix)
* Note: any unused input pins should be tied together and connected to ground with a capacitor (0.1 F suggested), except the MIC1 and MIC2 inputs which require their own 0.1 F capacitors to ground if not used. 4.2 Mixer Output The mixer generates two distinct outputs: * * * stereo mix of all sources for output to the LINE_OUT stereo mix of all sources for output to the LNLVL_OUT mono, MIC only or mix of all sources for MONO_OUT
* Note: Mono output of stereo mix is attenuated by -6 dB to prevent clipping when left and right channels are combined. 4.3 PC Beep Implementation PC Beep is active on power up and defaults to an un-muted state. The user should mute this input before using any other mixer input because the PC Beep input can contribute noise to the LINE_OUT during normal operation.
20 04/07/00
04/07/00
SigmaTel, Inc.
4.4 Programming Registers:
Data Sheet
Table 7. Programming Registers
STAC9721
REG #
00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 28h 6Ch 6Eh 70h 72h 74h 76h 78h 7Ch 7Eh
NAME
Reset Master Volume LNLVL Volume Master Volume Mono PC_BEEP Volume Phone Volume Mic Volume Line In Volume CD Volume Video Volume AUX Volume PCM Out Volume Record Select Record Gain General Purpose 3D Control Powerdown Ctrl/Stat Extended Audio ID Revision Code Analog Special 72h Enable Analog Current Adjust Multi-Channel Selection 78h Enable Clock Access Vendor ID1 Vendor ID2
D15 D14 D13 D12 D11 D10 D9
X Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute X Mute X X SE4 X X X X X X X X X X X X X X X SE3 SE2 X X X X X X X X X X X X X 3D X SE1 SE0 ID9
D8
ID8
D7
ID7 X X X X X X X X X X X X X
D6
ID6 X X X X X 20dB X X X X X X X X X X X 0 X
D5
ID5 X X X X X X X X X X X X X X X X X 0 X
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
DEFAULT
6940h 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Fh 0200h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 8384h 7609h
ML4 ML3 ML2 ML1 ML0 GL4 X X X X GL4 GL4 GL4 GL4 GL4 X X X X GL3 X X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X GL2 X X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X GL1 X X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX X GL0 X X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0
MR4 MR3 MR2 MR1 MR0 GR4 GR3 GR2 GR1 GR0 MM4 MM3 MM2 MM1 MM0 PV3 PV2 PV1 PV0 X
GN4 GN3 GN2 GN1 GN0 GN4 GN3 GN2 GN1 GN0 GR4 GR3 GR2 GR1 GR0 GR4 GR3 GR2 GR1 GR0 GR4 GR3 GR2 GR1 GR0 GR4 GR3 GR2 GR1 GR0 GR4 GR3 GR2 GR1 GR0 X X X X X X 0 X X SR2 SR1 SR0
GR3 GR2 GR1 GR0 X X X X X X
MS LPBK X X X X 0 X
DP3 DP2
EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 ID1 0 X ID0 0 X X 0 X X 0 X X 0 X X 0 X
AMAP
REF ANL DAC ADC X 0 X X 0 X X 0 X 0
X 0 X
0 X
DAC ADC -6dB -6dB
EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 X X X X X X X X X X X X X X X X X X X X X X X X X X Bias1 Bias0 X X
MC1 MC0
EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 X 1 0 X 0 1 ALT PWD CLK CLK CL2x INV 0 0 0 1 1 0 X 0 1 X 1 1 X 1 0 X 1 0 X 0 0 X 0 0 X 0 0 X 0 1 X 1 0 OSC PWD 0 0 X 0 1
Notes: 1. All registers not shown and bits containing an X are reserved. 2. Any reserved bits, marked X, are not writable, and read back as zeros. 3. PC_BEEP default to 0000h, un-muted. 4. If optional bits D13, D5 of register 02h or D5 of register 06h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block.
21 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
4.4.1 Reset Register (Index 00h) Writing any value to this register performs a register reset, which causes all registers to revert to their default values. This register returns the AC'97 ID code of the part when read. 4.4.2 Play Master Volume Registers (Index 02h, 04h, and 06h) These registers manage the output signal volumes. Register 02h controls the stereo master volume (both right and left channels), register 04h controls the optional stereo true line level out, and register 06h controls the mono volume output. Each step corresponds to 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. ML5 through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 through MM0 is for the mono out channel. If optional bits D13 and D5 of register 02h and 04h, or D5 of register 06h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block
Table 8. Play Master Volume Register Mute 0 0 1 Mx5...Mx0 00 0000 01 1111 xx xxxx Function 0dB Attenuation 46.5 Attenuation dB Attenuation Range Req. Req. Req.
4.4.3 PC Beep Register (Index 0Ah) This register controls the level for the PC Beep input. Each step corresponds to approximately 3 dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. PC_BEEP supports motherboard implementations. The intention of routing PC_BEEP through the STAC9721/23 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. In order for this to be viable the PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is routed to L & R Line outputs even when the STAC9721/23 is in a RESET state. This is so that Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. For further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The default value of 0000h corresponds to 0 dB attenuation with mute off.
Table 9. PC_BEEP Register Mute 0 0 1 PV3...PV0 0000 1111 xxxx Function 0 dB Attenuation 45 dB Attenuation dB Attenuation
22 04/07/00
04/07/00
SigmaTel, Inc.
4.4.4
Data Sheet
STAC9721
Analog Mixer Input Gain Registers (Index 0Ch - 18h) These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. Register 0Eh (Mic Volume Register) has an extra bit that is for a 20dB boost. When bit D6 is set to 1, the +20 dB boost is on. The default value is 8008, which corresponds to 0 dB gain, bost off, and mute on. The default value for the mono registers is 8008h, which is to 0dB gain with mute on. The default value for stereo registers is 8808h, which is 0 dB gain with mute on.
Table 10. Analog Mixer Input Gain Register Mute 0 0 0 1 Gx4...Gx0 00000 01000 11111 xxxxx Function +12 dB gain 0 dB gain -34.5 dB gain - dB gain
4.4.5
Record Select Control Register (Index 1Ah) Used to select the record source independently for right and left. The default value is 0000h, which corresponds to MIC in.
Table 11. Record Select Control Registers SR2...SR0 0 1 2 3 4 5 6 7 Right Record Source MIC CD In (right) Video In (right) Aux In (right) Line In (right) Stereo Mix (right) Mono Mix Phone
Table 12. Left Record Select Control Registers SL2...SL0 0 1 2 3 4 5 6 7 Left Record Source MIC CD In (L) Video In (L) Aux In (L) Line In (L) Stereo Mix (L) Mono Mix Phone
23 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
4.4.6 Record Gain Registers (Index 1Ch) The 1Ch register adjusts the stereo input record gain. Each step corresponds to 1.5 dB. The 22.5 dB setting corresponds to 0F0Fh. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel(s) is set at - dB. The default value is 8000h, which is to 0 dB gain with mute on.
Table 13. Record Gain Registers Mute 0 0 1 Gx3... Gx0 1111 0000 xxxx Function +22.5 dB gain 0 dB gain - gain
4.4.7 General Purpose Register (Index 20h) This register is used to control some miscellaneous functions. Below is a summary of each bit and its function. The MS bit controls the MIC1/MIC2 selector, and the MIX bit controls the Mix/MIC selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-Link, allowing for full system performance measurements. The 3D bit enables or disables the SS3D speaker separation 3D enhancement.
Table 14. General Purpose Register Bit 3D MIX MS LPBK Function
3D Stereo Enhancement 0 = off, 1 = on
Mono output select 0 = Mix, 1= MIC Mic select 0 = MIC1, 1 = MIC2 ADC/DAC loopback mode
24 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
4.4.7 3D Control Register (Index 22h) This register is used to control the 3D stereo enhancement function, SigmaTel Surround 3D (SS3D), built into the codec. SS3D provides for a wider soundstage and speaker separation for 2-speaker arrangements. Register bits, DP3-DP2 are used to control the separation ratios in the 3D control for LINE_OUT. The 3D bit in the general purpose register (register 20h bit D13) must be set to 1 to enable SS3D functionality and for the bits in 22h to take effect.
Table 15. 3D Control Registers DP3..DP0 LINE_OUT Separation Ratio 0 (Off) 3 (Low) 4.5 (Med.) 6.0 (High)
00XX 01XX 10XX 11XX
The three separation ratios are implemented as shown above. The separation ratio defines a series of equations that determine the amount of depth difference (High, Medium, and Low) perceived during two-channel playback. The ratios provide an indication of how much soundstage increase can be expected. 4.4.8 Powerdown Control/Status Register (Index 26h) This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is read only status, a "1" indicating that the subsection is "ready". Ready is defined as the subsection's ability to perform in its nominal state. When this register is written, bits D7:D0 will not be affected. Bit D15 controls the External Amplifier Power Down pin. When the AC-Link "Codec Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register (D3:D0) to determine exactly which subsections, if any are ready.
Table 16. Powerdown Status Registers BIT EAPD REF ANL DAC ADC FUNCTION External Amplifier Power Down Indicates VREF is at nominal level Analog mixers, etc. ready DAC section ready to playback data ADC section ready to playback data
25 04/07/00 04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
4.4.8.1 External Amplifier Power Down Control
The EAPD bit D15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of the EAPD output, pin 45, and produces a logical "1" when this bit is set to logic high. This function is used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVDD on the output pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility.Extended Audio ID Register (Index 28)
4.4.9 Extended Audio Register (Index 28h) The Extended Audio ID register is a read only register. ID1 and ID0 echo the configuration of the codec as defined by the programming of pins 45 and 46 externally. "00" returned defines the codec as the primary codec, while any other code identifies the codec as one of three secondary codec possibilities. The AMAP bit, D9, will return a 1 indicating that the codec supports the optional "AC'97 2.1 compliant AC-link slot to audio DAC mappings". The default condition assumes that 0, 0 are loaded in the MC1 and MC0 bits of the Multi-Channel Programming Register (Index 74h). With 0s in the MCx bits, the codec slot assignments are as per the AC'97 specification recommendations. If the MCx bits do not contain 0s, the slot assignments are as per the table in the section describing the Multi-Channel Programming Register (Index 74h).
Table 17. Extended Audio ID Register Functions BIT IDx AMAP FUNCTION External CID pin status Multi-channel slot support
4.4.10 Revision (Index 6Ch) The device Revision register (index 6Ch) contains a software readable revision-specific code used to identify performance, architectural, or software differences between various device revisions. Bits 7:0 of the Revision register are user readable; bits 15:8 are not used at this time and will return zeros when read. The lower order bits of the Revision Register (bits 7:0) are currently set to 00h, and will likely change if there are any STAC9721/23 metal revisions. 4.4.11 Analog Special Register (Index 6Eh) The Analog Special Register has two read/write bits used to control two functions specific to the STAC9721/23. DAC -6dB is used to program the DAC outputs to a -6dB signal level relative to the value of gain already programmed. Similarly, ADC -6dB attenuates any signal input to the ADC by 6dB.
26 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
4.4.12 Analog Current Adjust (Index 70h and 72h) The Analog Current Adjust register (index 72h) is a locked register and can only be properly written and read from when ABBAh has been written into register 70h. The BIASx bits allow the analog current to be adjusted with minimal reduction in performance. The -50% analog current setting is not recommended when a 5V analog supply is used. The -50% setting for 3.3V supplies is recommended to reduce power consumption for notebook computers to its lowest level.
Table 18: Analog Current Adjust BIAS1 0 0 1 1 BIAS0 0 1 0 1 Analog Current Normal Current -50% Analog Current -25% Analog Current +25% Analog Current
4.4.13 Multi-Channel Programming Register (Index 74h) This read/write register is used to program the various options for multi-channel configurations. Only the two LSBs are used (MC0 and MC1), and they define which AC-Link slot data is supplied to the two PCM output channels on the STAC9721/23. The purpose of using slot 10 and 11 in the final configuration is to allow for the possibility of an eight-channel architecture using several STAC9721/23 or STAC9708 devices in the multi-codec configuration. Also see "Multiple Codec Support" discussion for information on the use of external pins CID1 and CID0.
27 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
Table 19. Multi-Channel Programming Register
STAC9721
External Pins CID1, CID0
Extended Audio ID 28h ID1, ID0 0, 0
Codec Designation
MultiChannel Selection 74h MC1, MC0 0, 0 0, 1 1, 0 1, 1 0, 0 0, 1 1, 0 1, 1 0, 0 0, 1 1, 0 1, 1 0, 0 0, 1 1, 0 1, 1
PCM OUT Left
PCM OUT Right
CID1 = DVdd or floating, CID0 = DVdd or floating CID1 = DVdd or floating, CID0 = GND CID1 = GND, CID0 = DVdd or floating CID1 = GND, CID0 = GND
Primary, 00
0, 1
Secondary, 01
1, 0
Secondary, 10
1, 1
Secondary, 11
Slot 3 Slot 7 Slot 6 Slot 10 Slot 3 Slot 7 Slot 6 Slot 10 Slot 7 Slot 3 Slot 10 Slot 6 Slot 6 Slot 10 Slot 3 Slot 7
Slot 4 Slot 8 Slot 9 Slot 11 Slot 4 Slot 8 Slot 9 Slot 11 Slot 8 Slot 4 Slot 11 Slot 9 Slot 9 Slot 11 Slot 4 Slot 8
4.4.14 Clock Access (Index 76h and 78h) The Clock Access register (index 78h) is a locked register and can only be properly written and read from when ABBAh has been written into register 76h. The STAC9744/45 can operate as a remotely located secondary without a 24.576MHz master clock input or local crystal. The STAC9744/45 can synchronize to the BIT_CLK after a register adjustments. The first adjustment starts the synchronization process by enabling the ALTCLK D13, PWD CL2x D12, CLK INV D11, and OSC PWD D1 bits of register 78h. With this adjustment, the STAC9744/45 will operate remotely without the 24.576 MHz master clock signal and without a local crystal. The XTAL_IN input should be connected to DGND with a 10k or larger resistor. The reserved bits of register 78h should not be written to. 4.4.15 Vendor ID1 and ID2 (Index 7Ch and 7Eh) These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a SigmaTel, Inc. assigned code identifying the STAC9721/23. The ID1 register (index 7Ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the Microsoft ID code. The ID2 register (index 7Eh) contains the value 7609h, which is the third (76h) of the Microsoft ID code, and 09h which is the STAC9721/23 ID code. NOTE: The lower half of the Vendor ID2 register (index 7Eh) currently contains the value 09h identifying the STAC9721/23. This value can be used by the audio driver, or miniport driver in the case of WIN98, to adjust software functionality to match the feature-set of the STAC9721/23. This portion of the register will likely contain different
28 04/07/00 04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
values if the software profile of the STAC9721/23 changes, as in the case of silicon level device modifications. This will allow the software driver to identify any required operational differences between the existing STAC9721/23 and any future versions. 5. Low Power Modes
The STAC9721/23 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The power down options are listed in Table 18. The first three bits , PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADC's, DAC's and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. PR0 and PR1 control the PCM ADC's and DAC's only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4.
Table 20. Low Power Modes GRP Bits PR0 PR1 PR2 PR3 PR4 PR5 PR6 Function PCM in ADC's & Input Mux Powerdown PCM out DACs Powerdown Analog Mixer powerdown (Vref still on) Analog Mixer powerdown (Vref off) Digital Interface (AC-Link) powerdown (extnl clk off) Internal Clk disable LNLVL_OUT disable
Figure 11. Example of STAC9721/23 Powerdown/Powerup flow
PR0=1 ADCs off PR0 PR0=0 & ADC=1 PR1=0 & DAC=1 Default PR1=1 PR2=1 DACs off PR1 PR4=1 Analog off PR2 or PR3 PR2=0 & ANL=1 Digital I/F off PR4 Warm Reset Shut off Coda-link
Normal
Ready =1
Cold Reset
The above figure illustrates one example procedure to do a complete powerdown of STAC9721/23. From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9721/23 a piece at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9721/23 can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states. When a section is powered back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it.
29 04/07/00 04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
Figure 12. STAC9721/23 Powerdown/Powerup flow with analog still alive
PR0=1 ADCs off PR0 PR0=0 & ADC=1 PR1=0 & DAC=1 Warm Reset PR1=1 DACs off PR1 PR4=1 Digital I/F off PR4 Shut off Coda-link
Normal
The above figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through STAC9721/23 to the speakers, while most of the system in low power mode. The procedure for this follows the previous except that the analog mixer is never shut down.
30 04/07/00
04/07/00
SigmaTel, Inc.
6. MULTIPLE CODEC SUPPORT
Data Sheet
STAC9721
The STAC9721/23 provides support for the multi-codec option according to the Intel AC'97, rev 2.1 specification. By definition there can be only one Primary Codec (Codec ID 00) and up to three Secondary Codecs (Codec IDs 01,10, and 11). The Codec ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers.
6.1 Primary/Secondary Codec Selection
In a multi-codec environment the codec ID is provided by external programming of pins 45 and 46 (CID0 and CID1). The CID pin electrical function is logically inverted from the codec ID designation. The corresponding pin state and its associated codec ID are listed in the "Codec ID Selection" table. Also see slot assignment discussion, "Multi-Channel Programming Register (Index 74)".
Table 21. Codec ID Selection CID1 State CID0 State Codec ID Codec Status EXTENDED AUDIO ID, 28h ID1, ID0 0, 0 0, 1 1, 0 1, 1
+5V or floating +5V or floating 0V 0V
+5V or floating 0V +5V or floating 0V
00 01 10 11
Primary Secondary Secondary Secondary
6.1.1 Primary Codec Operation As a Primary device the STAC9721/23 is completely compatible with existing AC'97 definitions and extensions. Primary Codec registers are accessed exactly as defined in the AC'97 Component Specification and AC'97 Extensions. The STAC9721/23 operates as Primary by default, and the external ID pins (47 and 48) have internal pull-ups so that these pins may be left as no-connects for primary operation. When used as the Primary Codec, the STAC9721/23 generates the master AC-Link BIT_CLK for both the AC'97 Digital Controller and any Secondary Codecs. The STAC9721/23 can support up to 4, 10 K 50 pF loads on the BIT_CLK. This is to insure that up to 4 Codec implementations will not load down the clock output. 6.1.2 Secondary Codec Operation When the STAC9721/23 is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary Codec insures that everything on the AC-Link will be synchronous. As a Secondary device it can be defined as Codec ID 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).
31 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
6.2 Secondary Codec Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary Codec registers by using a 2-bit Codec ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary Codec access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0). As a Secondary Codec, the STAC9721/23 will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches its configuration. In a sense the Secondary Codec ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. Secondary Codecs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the Secondary Codec ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the Secondary Codec ID bits are set. This method is designed to be backward compatible with existing AC'97 controllers and Codecs. There is no change to output Slot 1 or 2 definitions.
Table 22. Secondary Codec Register Access Slot 0 Bit Definitions Output Tag Slot (16-bits) Bit 15 14 13 12-3
2
Description Frame Valid Slot 1 Valid Command Address bit (Primary Codec only) Slot 2 Valid Command Data bit (Primary Codec only) Slot 3-12 Valid bits as defined by AC'97 Reserved (Set to "0")
2-bit Codec ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary) New definitions for Secondary Codec Register Access
1-0
7.
TESTABILITY
The STAC9721/23 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel's internal use. STAC9721/23 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the STAC9704/7 must be issued another rest with all AC-link signals held low to return to the normal operating mode.
32 04/07/00
04/07/00
SigmaTel, Inc.
8.
Data Sheet
STAC9721
EXTENDED CODEC FUNCTIONALITY
8.1 Anti-Pop Circuitry
The STAC9721/23 provides an integrated output signal (APOP on pin 34) to aid in low-component-count anti-pop implementations. An audible speaker "pop" can occur when the main power is applied to, or removed from, the codec or audio output amplifier. In ac coupled systems, the speaker sided of the ac coupling capacitor is shunted to ground through a transistor or FET; this prevents audible pops when the system is powering on and off. A 10 F capacitor on CAP1 provides a delay to hold-off power to the output stages on power up. A 22 F capacitor provides reserve power to sustain the output shunting action until the power has been fully removed on power down. APOP is active logic high during shunting operations; APOP is at logic low during normal operations.
9.
AC TIMING CHARACTERISTICS (Tambient = 25 C, AVdd = DVdd = 5.0V or 3.3V 5%,
AVss=DVss+0V; 50pF external load)
9.1 Cold Reset
Figure 13. Cold Reset
Trst2clk Tres_low
RESET# BIT_CLK
Table 23. Cold Reset Parameter RESET# active low pulse width RESET# inactive to BIT_CLK startup delay
# denotes active low.
Symbol Tres_low Trst2clk
Min 1.0 162.8
Typ -
Max -
Units us ns
33 04/07/00
04/07/00
SigmaTel, Inc.
9.2 Warm Reset
Data Sheet
STAC9721
Figure 14. Warm Reset
Tsync_high Tsync_2clk
SYNC BIT_CLK
Table 24. Warm Reset Parameter SYNC active high pulse width SYNC inactive to BIT_CLK startup delay Symbol Tsync_high Tsync2clk Min 1.0 162.8 Typ 1.3 Max Units us ns
9.3 Clocks
Figure 15. Clocks
Tclk_low
BIT_CLK
Tclk_high
Tclk_period Tsync_low
SYNC
Tsync_high
Tsync_period
Table 25. Clocks Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulsewidth (note 1) BIT_CLK low pulse width (note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low_pulse width
Notes: 1) Worst case duty cycle restricted to 40/60. 34 04/07/00 04/07/00
Symbol Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low
Min 36 36 -
Typ 12.288 81.4 40.7 40.7 48.0 20.8 1.3 19.5
Max 750 45 45 -
Units MHz ns ps ns ns kHz us us us
SigmaTel, Inc.
9.4 Data Setup and Hold
Data Sheet
(50pF external load)
STAC9721
Figure 16. Data Setup and Hold
Tsetup
BIT_CLK SDATA_IN SDATA_OUT
Thold
SYNC
Tsetup Thold
Table 26. Data Setup and Hold Parameter Setup to falling edge of BIT_CLK Hold from falling edge of BIT_CLK Symbol Tsetup Thold Min 10 10 Typ Max Units ns ns
Note 1: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.
9.5 Signal Rise and Fall Times - (50pF external load; from 10% to 90% of Vdd)
Figure 17. Signal Rise and Fall Times
BIT_CLK
Triseclk Tfallclk
SDATA_IN
Trisedin Tfalldin
Table 27. Signal Rise and Fall Times Parameter BIT_CLK rise time BIT_CLK fall time SDATA_IN rise time SDATA_IN fall time Symbol Triseclk Tfallclk Trisedin Tfalldin Min 2 2 2 2 Typ Max 6 6 6 6 Units ns ns ns ns
35 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
9.6 AC-Link Low Power Mode Timing
Figure 18. AC-Link Low Power Mode Timing
SYNC BIT_CLK SDATA_OUT SDATA_IN
Slot 1
Slot 2
Write to 0x20
Data PR4
Don't care Ts2_pdown
Note: BIT_CLK not to scale
Table 28. AC-Link Low Power Mode Timing Parameter End of Slot 2 to BIT_CLK, SDATA_IN low Symbol Ts2_pdown Min Typ Max 1.0 Units us
36 04/07/00
04/07/00
SigmaTel, Inc.
9.7 ATE Test Mode
Data Sheet
STAC9721
Figure 19. ATE Test Mode
RESET# SDATA_OUT SDATA_IN, BIT_CLK
Toff
Tsetup2rst Hi-Z
Table 29. ATE Test Mode Parameter Setup to trailing edge of RESET# (also applies to SYNC) Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Symbol ToffTsetup2rst Tsetup2rst Toff Min 15.0 15.0 Typ Max 25.0 Units ns ns ns
Notes: 1. All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge of RESET# causes STAC9721/23's AC-Link outputs to go high impedance which is suitable for ATE in circuit testing. 2. Once either of the two test modes have been entered, the STAC9721/23 must be issued another RESET# with all AC-Link signals low to return to the normal operating mode. # denotes active low.
37 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
10. ELECTRICAL SPECIFICATIONS: 10.1 Absolute Maximum Ratings:
Vss - 0.3V TO Vdd + 0.3V 0 oC TO 70 o C oC TO +125 o C -55 260 oC FOR 10 SECONDS
Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin
4 mA except Vrefout = 5mA
10.2
Recommended Operating Conditions
Table 30. Operating Conditions PARAMETER Power Supplies + 3.3V Digital + 5V Digital + 5V Analog + 3.3V Analog MIN 3.135 4.75 4.75 3.135 0 TYP 3.3 5 5 3.3 MAX UNITS 3.465 5.25 5.25 3.465 70 V V V V oC
Ambient Temperature
SigmaTel reserves the right to change specifications without notice.
38 04/07/00
04/07/00
SigmaTel, Inc.
10.3 Power Consumption
Data Sheet
STAC9721
Table 31: Power Consumption at Default Analog Current PARAMETER Digital Supply Current + 5V Digital: DAC and ADC Active + 3.3V Digital: DAC and ADC Active + 3.3V Digital: DAC and ADC Muted Analog Supply Current + 5V Analog: PC_BEEP Muted + 3.3V Analog: PC_BEEP Muted Power Down Status PR0 +5V Analog Supply Current PR1 +5V Analog Supply Current PR2 +5V Analog Supply Current PR3 +5V Analog Supply Current PR0,1,2,3 +5V Analog Supply Current PR4 +3.3V Digital Supply Current PR4 +5V Digital Supply Current PR5 No Effect MIN TYP 30 20 7 38 34 28 37 28 1.1 0.6 0.1 0.1 MAX UNITS mA mA mA mA mA mA mA mA mA mA mA mA
Table 32: Power Consumption at 3.3V Analog, Low Current Mode* PARAMETER Digital Supply Current + 3.3V Digital with DAC and ADC Active Analog Supply Current + 3.3V Analog with DAC and ADC Muted Power Down Status PR0 +3.3V Analog Supply Current PR1 +3.3V Analog Supply Current PR2 +3.3V Analog Supply Current PR3 +3.3V Analog Supply Current PR0,1,2,3 +3.3V Analog Supply Current PR4 +3.3V Digital Supply Current PR5 No Effect MIN TYP 20 19 15 19 15 0.4 0.4 0.1 MAX UNITS mA mA mA mA mA mA mA mA
* -50% Analog Current Setting (Recommended for 3.3V Analog only): Register 70h=ABBAh, 72h=0002h
39 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
STAC9721
Table 33: Reduced Analog Power Settings Typical Supply Current Condition Default Analog Current Reset All Un-Muted ADC, LINE Thru, PC_BEEP active DAC, LINE Thru, PC_BEEP active All but DAC and ADC -25% Analog Current Reset All Un-Muted ADC, LINE Thru, PC_BEEP active DAC, LINE Thru, PC_BEEP active All but DAC and ADC -50% Analog Current Reset All Un-Muted ADC, LINE Thru, PC_BEEP active DAC, LINE Thru, PC_BEEP active All but DAC and ADC +25% Analog Current Reset All Un-Muted ADC, LINE Thru, PC_BEEP active DAC, LINE Thru, PC_BEEP active All but DAC and ADC 3.3V Analog 30 65 36 51 41 24 52 29 41 33 17 38 21 30 24 35 75 43 54 48 5V Analog 40 82 60 57 47 32 67 50 46 37 This Setting Not Recommended
46 94 69 67 55
40 04/07/00
04/07/00
SigmaTel, Inc.
10.4
AVss=DVss=0V; 50pF external load)
Data Sheet
STAC9721
AC-Link Static Digital Specifications (Tambient = 25 oC, DVdd = 5.0V or 3.3V 5%,
Table 34. AC-Link Static Specifications PARAMETER SYMBOL Vin Vil Vih Voh Vol MIN -0.30 0.65xDVd d 0.90xDVd d -10 -10 5 TYP MAX DVdd + 0.30 0.35xDVdd 0.1xDVdd 10 10 UNITS V V V V V uA uA mA
Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (Hi-Z'd AC-Link outputs) Output buffer drive current
10.5
= 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10K/50pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages) Table 35. Analog Performance Characteristics PARAMETER Full Scale Input Voltage: Line Inputs Mic Inputs1 Full Scale Output Voltage: Line Output 5V Analog S/N: CD to LINE_OUT 5V Other to LINE_OUT 5V Analog Frequency Response2 Digital S/N D/A 5V A/D 5V Digital S/N3 D/A 5V A/D 5V Total Harmonic Distortion: Line Output4 D/A & A/D Frequency Response5 Transition Band Stop Band Stop Band Rejection
6 3
STAC9721 Analog Performance Characteristics (Tambient = 25 oC, AVdd = 5.0V 5%, DVdd
MIN 90 20 85 75 85 75 20 19,200 28,800 +85
TYP 1.0 0.1 1.0 98 98 96 87 96 86 -
MAX 20,000 0.02 19,200 28,800 -
UNITS Vrms Vrms dB Hz dB dB % Hz Hz Hz dB
41 04/07/00
04/07/00
SigmaTel, Inc.
Out-of-Band Rejection7 Group Delay
Data Sheet
10 +40 +40 +100 1.5 15 0.5 x AVdd 100 10 10 90 96 50 1 - 1 - -70 - - - - - 0.5 0.5
STAC9721
dB ms dB dB dB dB K pF V dB dB ppm/deg. C mV degree K ohm dB
Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (Vrms input)
Notes: With +20 dB Boost on, 1.0Vrms with Boost off 1 dB limits The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 5. 0.25dB limits 6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output.
1. 2. 3.
42 04/07/00
04/07/00
SigmaTel, Inc.
10.6
Data Sheet
STAC9721
STAC9723 Analog Performance Characteristics (Tambient = 25 oC, AVdd = DVdd = 3.3V
5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10K/50pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages) Table 36. Analog Performance Characteristics PARAMETER Full Scale Output Voltage: Line Inputs to line output 3.3V Line Inputs to LINE_OUT 3.3V @ Line In = 1 Vrms and @ Gain setting of 4.5-6 dB Line Inputs to LINE_OUT 3.3V @ Line In = 0.6 5 Vrms and @ gain setting of 0dB PCM to LINE_OUT 3.3V @ full scale PCM input @PCM gain setting of 0dB PCM to Line Output 3.3V MIC Inputs to LINE_OUT 3.3V @ MIC In = 1 Vrms and @ gain setting of 0dB Full Scale Output Voltage: Line Inputs to line output 3.3V Line Inputs to LINE_OUT 3.3V @ Line In = 1 Vrms and @ Gain setting of -6 dB Line Inputs to LINE_OUT 3.3V @ Line In = 0.5 Vrms and @ gain setting of 0dB PCM to LINE_OUT 3.3V @ full scale PCM input @PCM gain setting of 0dB PCM to Line Output 3.3V MIC Inputs to LINE_OUT 3.3V @ MIC In = 1 Vrms and @ gain setting of 0dB Analog S/N: CD to LINE_OUT 3.3V Other to LINE_OUT 3.3V Analog Frequency Response2 Digital S/N D/A 3.3V A/D 3.3V Total Harmonic Distortion: Line Output4 D/A & A/D Frequency Response5 Transition Band Stop Band Stop Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance
43 04/07/00
6 7 3
MIN -
TYP 0.65 0.65 0.65 0.555 0.5
MAX -
UNITS Vrms Vrms Vrms Vrms Vrms
-
0.5 0.5 0.5 0.5 0.5
-
Vrms Vrms Vrms Vrms Vrms
20 85 75 20 19,200 28,800 +85 10 -
90 90 90 85 +40 +40 +100 1.5 15
20,000 0.02 19,200 28,800 - - 1 - -70 - - - - % Hz Hz Hz dB dB ms dB dB dB dB K pF
04/07/00
Hz
Out-of-Band Rejection
SigmaTel, Inc.
Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (0 dB)
Data Sheet
0.5 x AVdd 100 10 10 90 96 50 1 - 0.5 0.5
STAC9721
V dB dB ppm/ oC mV degree K dB
Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. 1 dB limits 3. The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 5. 0.25dB limits 6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output.
44 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
Appendix A
STAC9721
SPLIT INDEPENDENT POWER SUPPLY OPERATION In PC applications, one power supply input to the STAC9721/23 may be derived from a supply regulator (as shown in Figure 3) and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on-chip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip SCR type latch-up. SigmaTel's STAC9721/23 specifically allows power-up sequencing delays between the analog (AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with no adverse effects to the codec. The IC is designed with independent analog and digital circuitry that prevents on-chip SCR type latch-up. .
3.3V or 5V 5% 0.1uF 1uF 0.1uF 38 AVdd2 1 DVdd1 9 DVdd2 XTL_IN 12 24.576MHz PC_BEEP XTL_OUT 13 14 AUX_L 15 AUX_R 16 VIDEO_L BIT_CLK 8 SDATA_IN 10 SYNC 11 RESET 45 CID0 46 CID1 EMI Filter 27pF PHONE 3 27pF SDATA_OUT 5 6 22 ohms 2 27pF 3.3V or 5V 5% 0.1uF
10uF
0.1uF
25 AVdd1
17
18
VIDEO_R CD_L
SigmaTel STAC9721/23
19 CD_GND
20 CD_R 21 27 Vref 0.1uF 28 Vrefout Optional Anti-Pop Circuit CAP1 31 33 1uF
MIC1
22
MIC2
23
LINE_IN_L
CAP3
10uF 100uF
24 32
LINE_IN_R
APOP CAP2 EAPD LINE_OUT_L LINE_OUT_R AFILT1 37 MONO_OUT 47 35 36 34
0.1uF
1uF
820pF
29
820pF
30
AFILT2
AVss1
26
AVss2 42
DVss1 4
DVss2 7
LNLVL_OUT_L 39
LNLVL_OUT_R 41 ** Teminate ground plane as close to power supply as possible
NOTE: Pins 31, 33, 34, 40
43, 44, and 48 are No Connects
Analog Gnd
Digital Gnd
45 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
Appendix B
STAC9721
+5.0V/+3.3V POWER SUPPLY OPERATION NOTES
The STAC9721 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though the STAC9721 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC Link Electrical Characteristics in this data book), we recommend that all digital interface signals to the AC-Link be 5V. If digital interface signals below 5V are used, then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity. The STAC9721 can also operate from a 3.3V digital supply connected to DVdd while maintaining a 5V analog supply on AVdd. On-chip level shifters ensure accurate logic transfers between the analog and digital portions of the STAC9721. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-chip ESD protection diodes from turning on. (See Appendixes A concerning SPLIT INDEPENDENT POWER SUPPLY OPERATION). The STAC9723 must be run from a 3.3V supply connected to both DVdd and AVdd. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-ship ESD protection diodes from turning on. *Always operate the STAC97xx digital supply from the same supply voltage as the digital controller supply. *All the analog inputs must be ac-coupled with a capacitor of 0.1 F or greater. It is recommended that a resistor of about 47K be connected from the signal side of the capacitor to analog GND as shown below.
> 1.0 uF SIGNAL 47K Analog Input
*All the analog outputs must be ac-coupled. If an external amplifier is used, make sure that the input impedance of the amplifier is at least 10K and use an ac-coupling capacitor of 1.0 F.
46 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
- NOTES -
STAC9721
47 04/07/00
04/07/00
SigmaTel, Inc.
Data Sheet
For more information, please contact:
STAC9721
SigmaTel, Inc.
6101 W. Courtyard Dr., Bldg. 1, Suite 100 Austin, Texas 78730 Tel (512) 343-6636x29, Fax (512) 343-6199
email: sales@sigmatel.com
http://www.sigmatel.com
48 04/07/00 04/07/00

▲Up To Search▲

Price & Availability of STAC9721T

	To Download STAC9721T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .